1. Field of the Invention
The present invention relates to a broadcasting receiver for a digital television (DTV), and more particularly, to a carrier recovery apparatus in a vestigial sideband modulation (VSB) type DTV broadcasting receiver.
2. Discussion of the Related Art
A vestigial sideband modulation (VSB) of Grand Alliance has been selected as a standard for digital television (DTV) transmission system in America and Korea. The grand alliance VSB is a method for modulating one of sidebands generated by amplitude-modulating a signal. That is, in the grand alliance VSB, a signal is amplitude-modulated in order to generate two sidebands with a carrier wave as a center, one of sidebands is attenuated and a remained sideband is modulated.
That is, the grand alliance VSB is one of methods effectively using a band by obtaining a spectrum of one sideband in a baseband and shifting it to passband.
When a signal is modulated according to VSB, a DC spectrum of the baseband is shifted to the passband and thus the DC spectrum is changed to a tone spectrum. This signal is commonly called as a pilot signal. A broadcasting station transmits the pilot signal to a receiver with a modulated signal for accurately demodulating the modulated signal at the receiver when a signal is modulated according to the VSB in the broadcasting station.
FIG. 1 is a block diagram illustrating a transmitter using a vestigial sideband modulation (VSB) adopted in an advanced television systems committee (ATSC).
By referring to FIG. 1, the transmitter includes a randomizer 101, a Reed-Solomon encoder (RS-encoder) 102, a data interleaver 103, a trellis encoder 104, a multiplexer 105, a pilot inserter 105, a VSB modulator 107 and a radio frequency (RF) up-converter 108.
The randomizer 101 randomly outputs data to the RS-encoder 102 for generating a white symbol.
The RS-encoder 102 encodes the randomly inputted data according to a Reed Solomon (RS) encoding method for an inside and a outside channel coating and additionally inserts 20 bytes parity code in to the RS encoded data. After inserting, the RS-encoder 102 outputs the RS encoded data to the interleaver 103.
The interleaver 103 interleaves the RS-encoded data according to a predetermined rule. After interleaving, the interleaver 103 outputs the interleaved data to the trellis encoder 104. The trellis encoder 104 converts the interleaved data from a byte to a symbol and encodes the converted symbol for generating a trellis encoded symbol sequence. After trellis encoding, the trellis encoded symbol sequence is outputted to the multiplexer 105
The multiplexer 105 muxes the trellis encoded symbol sequence, a segment synchronizing signal and a field synchronizing signal at each segment and each frame for generating a frame. The multiplexer 105 outputs the generated frame to the pilot inserter 105.
The pilot inserter 105 inserts a pilot signal which is a DC value in the framed transmitting symbol and outputs the pilot symbol inserted frame to the VSB modulator 107.
A construction of the randomizer 101, the RS-encoder 102, the interleaver 103, the trellis encoder 104, the multiplexer 105 and the pilot inserter 106 is called as a channel encoder.
The VBS modulator 107 receives the encoded digital signal outputted from the channel encoder and modulates the encoded digital signal to VSB intermediate frequency signal having 6 MHz bandwidth by the VSB modulator 107. The modulated signal is outputted to the RF up-converter 108. The RF up-converter 108 converts the modulated signal to a RF passband signal and the RF passband signal is transmitted through a transmitting antenna 109.
FIG. 2 is a detailed diagram showing the VSB modulator 107 in FIG. 1.
As shown in FIG. 2, the VSB modulator includes a complex filter 201, an intermediate frequency converter 202 and a subtractor 203.
The encoded digital signal outputted from the channel encoder is inputted to the complex filter 201 for VSB modulation. When the encoded digital signal is passed through the complex filter 201, forms of frequencies of I and Q signals are changed for VSB modulation.
The intermediate frequency modulator 202 modulates each of I and Q signals to an intermediate frequency I signal and an intermediate frequency Q signal (fc) and outputs the intermediate frequency I signal and the intermediate frequency Q signal to the subtractor 203.
The subtractor 203 subtracts the intermediate frequency Q signal from the intermediate frequency I signal for generating VSB intermediate signal having 65 MHz bandwidth.
The RF up-converter 108 converts the VSB intermediate signal from the subtractor 203 to a RF passband signal and the RF passband signal is transmitted through the antenna 109 to a receiver.
As mentioned above, the transmitter transmits the VSB intermediate signal with the pilot signal to the receiver through a transmission channel by modulating the signal and inserting the pilot signal into the modulated signal in the VSB modulator 107. Therefore, the receiver can accurately demodulate the VSB intermediate signal by using a carrier recovery unit in the receiver.
FIG. 3 is a graph showing a frequency characteristic of sky wave signal defined by a digital television (DTV) standard in America and Korea. A center frequency (fc) and a pilot frequency (fp) are different according to each channel. But, in FIG. 3, the center frequency is described as fc and the pilot frequency is described as fp.
For example, the center frequency fc is a middle of frequency in 6 MHz bandwidth of each ground channel and the pilot frequency fp is a frequency including a carrier signal in a transmitting signal. A reason for using a pilot signal instead of carrier signal is that intensity of carrier signal is reduced as much as 13 dB in order to avoid influencing the analog TV signal.
Accordingly, the carrier recovery unit in the DTV receiver accurately recovers a location of the pilot frequency fp in frequency of the transmitting signal and the recovered pilot frequency is converted to a baseband signal.
General algorithm used in the carrier recovery unit is a digital frequency phase loop lock (DFPLL) algorithm. The DFPLL algorithm has several advantages. That is, it is easy to be implemented as a circuit and has superior performance.
The carrier recovery unit based on the DFPLL receives a passband I signal and a passband Q signal from an A/D converter located in front of the carrier recovery unit and demodulates the passband I signal and the passband Q signal for locking the phase and frequency of the passband I and Q signals.
The DFPLL performs a frequency locked loop for eliminating frequency difference between the carrier wave of the receiving signal and a reference carrier wave of the receiver and then performs a phase locked loop (PLL) for eliminating phase difference between two carrier waves where the frequency difference eliminated.
FIG. 4 is a block diagram illustrating a carrier recovery apparatus based on DFPLL in accordance with a related art.
As shown in FIG. 4, the carrier recovery apparatus includes a phase divider 501, a complex multiplier 502, a frequency phase error detector (FPED) 503, a loop filter 504, a numerically controlled oscillator (NCO) 505.
By referring to the FIG. 4, the phase divider 501 receives a digitalized signal from an AID converter located in front of the phase divider 501 and divides the digitalized signal to an I passband signal and a Q passband signal by multiplying the received digitalized signal to an I component and a Q component. The I and the Q signals are outputted to the complex multiplier 502.
The complex multiplier 502 receives a complex carrier which is carrier recovered from the numerically controlled oscillator (NCO) 505. That is, the complex multiplier 502 receives a sine wave (SIN) and a cosine wave (COS) from the NCO 505. The complex multiplier 502 multiplies the complex carrier to the I and the Q passband signals from the phase divider 501 for shifting the I and the Q passband signals to an I baseband signal and a Q baseband signal.
The I baseband signal and the Q baseband signal are outputted to a DC eliminator located at back of the carrier recover apparatus and simultaneously outputs to the frequency phase error detector (FPED) 503 for carrier recovery.
The FPED 503 includes a first and a second low pass filters 503a, 503b, a delay 503c, a sign extractor 503d and a multiplier 503e. 
The first low pass filter 503a receives the I baseband signal from the complex multiplier 502 and the second low pass filter 503b receives the Q baseband signal from the complex multiplier 502.
Inhere, the carrier recovery apparatus requires a signal around frequency including a pilot frequency (fp) in 6 MHz bandwidth. Therefore, the first and the second low pass filters 503a, 503b eliminates frequency components including data components from the I baseband signal and the Q baseband signal for preventing a performance degradation of the carrier recovery apparatus by data.
In other words, the pilot signal in the I and Q baseband signals is changed to a DC component. In more detail, they are changed to frequency component around DC component.
It is generated by component difference between a carrier wave generated at the NCO 505 and a carrier wave component of the inputted signal. Accordingly, data component excepting the component around DC is eliminated by the first and the second low pass filters 503a and 503b since components around DC is required for recovering the carrier wave.
The output signal of the first low pass filter 503a is inputted to the delay 503c. 
The delay 503c delays the data component eliminated I signal from the first filter 503a as long as a predetermined time and outputs the delayed I signal to the sign extractor 503d. During delaying, if the pilot component of I signal outputted from the first low pass filter 503a is not exactly changed to the target DC components during passing the delay 503c, the phase error is generated as much as the difference between the target DC component and the delayed pilot component of I signal.
Accordingly, the delay 503c converts difference between the pilot component of the inputted passband signal and the carrier frequency component of NCO 505 to a phase error and outputs the phase error to the sign extractor 503d. 
The sign extractor 503d extracts a sign of the signal outputted from the delay 503c and outputs the extracted sign in a form of 1 or −1 to the multiplier 503e. The multiplier 503e multiplies the extracted sign of the I signal and the data component eliminated Q signal and outputs the multiplying result as a phase error to the loop filter 504.
The loop filter 504 filters the phase error from the multiplier 503e and integrates the filtered phase error. The integrated phase error is outputted to the NCO 505. The NCO 505 generates a complex carrier (COS, SIN) corresponding to the output of the loop filter 504 and outputs the generated complex carrier to the complex multiplier 502.
According to the above mentioned procedure, the complex carrier becomes similar to the carrier frequency components of the received signal.
By repeating the above mentioned procedure, the NCO 505 generates the carrier frequency signal having similar to the carrier frequency component of received signal and outputs the generated carrier frequency signal to the complex multiplier 502. The complex multiplier 502 shifts the passband signal to the baseband signal.
That is, if the pilot frequency of the inputted carrier signal component and the frequency component of the carrier signal generated in the NCO 505 are exactly matched, the PLL is completed.
However, they could not be exactly matched because of characteristics of the NCO 505 and characteristics of transmission line.
Accordingly, the carrier recovery apparatus compensates the unmatched frequency components and changes a frequency of the NCO 505 for matching the frequencies of two carrier signals.
That is, before completing the PLL, the sign extractor 503d alternatively outputs 1 and −1 and after completing the PLL, the sign extractor selects one of 1 and −1 and continuously outputs selected one.
When the sign extractor 506 outputs constant sign, the first low pass filter 503a, the delay 503c and the sign extractor 503d are stopped to be operated and the second low pass filter 503c is only operated. That is, if the PLL is completed, a phase locked loop (PLL) is automatically performed for eliminating a phase error between two carrier signals.
The above mentioned DFPLL has simple construction, a superior frequency lock performance and high stability.
FIGS. 5a to 5c are graphs showing wave forms for explaining principle of FLL operation in a carrier recovery unit in accordance with a related art.
In FIGS. 5a to 5c, A(t), B(t), B′(t), B″(t) and c(t) represent output signals of the second low pass filter 503b, the first low pass filter 503a, the delay 503c, the sign extractor 503d and the multiplier 503e in FIG. 4, respectively.
FIG. 5a shows waveforms when an input frequency fc of the carrier recovery unit 306 is identical to an output frequency fc′ of the NCO 505 (fc′=fc) and the output signal of the second low pass filter 503b is a cosine signal form and the output signal of the first low pass filter 503a is a sine signal form.
That is, because the input frequency fc of the carrier recovery unit 306 is identical to an output frequency fc′ of the NCO 505, the delay 503c outputs the output signal of the first low pass filter 503a without delaying. Accordingly, the output signal B(t) of the first low pass filter 503a and the output signal B′(t) of the delay 503c are identical.
The output signal B′(t) of delay 503c is analyzed at the sign extractor 503d for detecting a sign of the signal. That is, if the output signal B′(t) is in a range of 0 degree to 180 degree, the sign extractor 503d outputs a signal of 1 and if the output signal B′(t) is in a range of 180 degree to 360 degree, the sign extractor 503d outputs a signal of −1.
Therefore, The multiplier 503e alternatively outputs the output signal C(t) having a negative value or the output signal C(t) having a positive value since the multiplier 503e multiplies the output signal B′(t) of the sign extractor 503d and the output signal A(t) of the second low pass filter. Accordingly, the FPED 503 outputs a signal having 0 as a DC value.
FIG. 5b shows waveforms when the input frequency fc of the carrier recovery unit 306 is smaller then the output frequency fc′ of the NCO 505 (fc<fc′), and the output signal A(t) of the second low pass filter 503b is a cosine signal form and the output signal of the first low pass filter 503a is a sine signal form.
As shown in FIG. 5b, the delay 503c converts a difference between fc and fc′ to a phase error and output the phase error because the input frequency fc of the carrier recovery unit 306 is smaller then the output frequency fc′ of the NCO 505.
In an example of the FIG. 5b, the delay 503c delays the output signal B(t) of the first low pass filter 503a as much as −90 degree and outputs the signal B′(t).
The output signal B′(t) of the delay 503c is analyzed at the sign extractor 503d for detecting sign of the signal. That is, if the output signal B′(t) is in a range of 0 degree to 90 degree, the sign extractor 503d outputs a signal of −1, if the output signal B′(t) is in a range of 90 degree to 270 degree, the sign extractor 503d outputs a signal of I and if the output signal B′(t) is in a range of 270 degree to 360 degree, the sign extractor 503d outputs a signal of −1.
Accordingly, the multiplier 503e always outputs the output signal C9t) having a negative value and the FPED 503 outputs a signal having a negative DC value.
FIG. 5c shows waveforms when the input frequency fc of the carrier recovery unit 306 is larger then the output frequency fc′ of the NCO 505 (fc>fc′), and the output signal A(t) of the second low pass filter 503b is a cosine signal form and the output signal of the first low pass filter 503a is a sine signal form.
As shown in FIG. 5b, the delay 503c converts a difference between fc and fc′ to a phase error and output the phase error because the input frequency fc of the carrier recovery unit 306 is larger then the output frequency fc′ of the NCO 505.
In an example of the FIG. 5b, the delay 503c delays the output signal B(t) of the first low pass filter 503a as much as +90 degree and outputs the signal B′(t).
The output signal B′(t) of the delay 503c is analyzed at the sign extractor 503d for detecting sign of the signal. That is, if the output signal B′(t) is in a range of 0 degree to 90 degree, the sign extractor 503d outputs a signal of 1, if the output signal B′(t) is in a range of 90 degree to 270 degree, the sign extractor 503d outputs a signal of −1 and if the output signal B′(t) is in a range of 270 degree to 360 degree, the sign extractor 503d outputs a signal of 1.
Accordingly, the multiplier 503e always outputs the output signal C(t) having a positive value and the FPED 503 outputs a signal having a positive DC value.
As mentioned above, the FLL is operated according to the sing extracted from the sign extractor 503d and locks the frequency as a result of the FLL. Accordingly, the pilot component is located at a DC. Inhere, the first low pass filter output constant DC value closed to 0 and accordingly, the sign extractor 503d continuously outputs one of +1 or −1 according to a polarity of the input signal.
If the sign extractor 503d continuously outputs one of +1 or −1 according to a polarity of the input signal, the FLL operation is completed and the PLL is performed.
As mentioned above, in the receiving system, a state of frequency lock in the carrier recovery unit can be recognized by an accumulated output value of the sign extractor 503d 
That is, the sign extractor 503d alternatively outputs + value or − value before locking the frequency and the sign extractor 503d continuously outputs one of + value or − value after locking frequency.
An accumulator (not shown) accumulates the sign value outputted from the sign extractor 503d and if the accumulated sign value is exceed over a predetermined threshold value, the accumulator notices the locking of frequency.
FIG. 6 is a view for explaining a method for locking frequency in a carrier recover unit in accordance with a related art. In FIG. 6, a sign determination level is a reference location for determining the polarity of a signal at the sign extractor 503d and it is located at 0.
Also, ‘+ threshold value’ and ‘− threshold value’ are reference locations for determining whether a frequency locking is completed or not in the carrier recovery unit. That is, if accumulated sign value is larger than ‘+ threshold value’, the frequency lock is completed as + polarity. Also, if accumulated sign value at the accumulator is smaller than ‘− threshold value’, the frequency lock is completed as − polarity.
FIGS. 7a and 7b are graphs showing waveforms of I and Q signals outputted from the first and the second low pass filters at a channel having no ghost in accordance with a related art. And, FIGS. 8a and 8b are graphs showing waveforms of output signal from the signal extractor at a channel having no ghost in accordance with a related art.
As shown in FIG. 7a, when a polarity of the I signal is ‘+’, the first low pass filter 503 alternatively outputs signals of ‘+’ sign or ‘−’ sign until the frequency lock is achieved. After achieving the frequency lock, the first low pass filter 503 outputs a DC pilot signal (I signal) having larger than the sign determination level (0). And the second low pass filter 504 outputs a Q signal located around the 0 value.
Accordingly, the sign extractor 506 alternatively outputs 1 or −1 initially and then continuously outputs I after a certain point as shown in FIG. 8a. 
In contrary, as shown in FIG. 7b, when a polarity of the I signal is ‘−’, the first low pass filter 503 alternatively outputs signals having ‘+’ sign or ‘−’ sign until the frequency lock is achieved. After achieving the frequency lock, the first low pass filter 503 outputs a DC pilot signal (I signal) having smaller value than the sign determination level(0). And the second low pass filter 504 outputs a Q signal located around the 0 value.
Accordingly, the sign extractor 506 alternatively outputs 1 or −1 initially and then continuously outputs −1 after a certain point as shown in FIG. 8b. 
As mentioned above, in case of no ghost existed in the channel, the sign extractor 506 continuously outputs a signal of +1 or a signal of −1 according to the polarity of the input signal.
When the sign extractor 506 continuously outputs one of +1 or −1, it represents that the FLL mode operation is completed and the PLL mode operation is automatically performed.
However, when the pilot signal becomes weaken during passing through the channel, the output signal of the first low pass filter 503a becomes weaken too. Therefore, the sign extractor may have difficulty to extract a sign of the output signal from the first low pass filter 503a. 
FIGS. 9a and 9b are graphs showing waveforms of output signal from the first low pass filter in accordance with a related art. And, FIG. 9c is a graph showing a waveform of output signal of the sign extractor at a channel having no ghost in accordance with a related art.
As shown in FIG. 9a, the output signals of the first low pass filter 503 are maintained to have average + value when a polarity of I signal is a positive (+). However, the output signal of the first low pass filter 503 becomes − value when the pilot signal becomes weaken according to the ghost. That is, the value of the output signal becomes crossed over the sign determination level 0(zero). It is commonly called as a zero-crossing.
In contrary, as shown in FIG. 9b, the output signals of the first low pass filter 503 are maintained to have average − value when a polarity of I signal is a negative (−). However, the output signal of the first low pass filter 503 becomes to + value when the pilot signal becomes weaken according to the ghost. That is, the value of the output signal becomes crossed over the sign determination level 0(zero).
By the zero-crossing, the sign extractor may alternatively output a signal having + value or a signal having − value as shown in FIG. 9C. And it may cause difficulty to the frequency lock.
Accordingly, the receiver may continuously stay in the FLL mode without changing to the PLL mode.
Furthermore, if the FLL mode is changed to the PLL mode, the sign extractor 506 may outputs signal having variable signs caused by changes in the channel. That is, the output signal of the sign extractor 506 may be changed from + value signal to − value signal or from − value signal to + value signal. Therefore, the PLL mode is unexpectedly changed to the FLL mode and it may degrade the performance of frequency lock.